1. Field of the Present Invention
The present invention relates to a test mode switching system for a large scale integration circuit or LSI to be connected to a central processing unit or CPU. The system is incorporated in the LSI to check whether or not the LSI can operate normally before leaving the factory.
2. Description of the Prior Art
In the prior art, LSI can be switched to a test mode through an external terminal of the LSI serving as a test mode switching pin of LSI as mentioned below. If the test mode pin is `1` condition which represents the test mode, the test signal data register incorporated in the LSI operates, storing test signal data inputted from the CPU through the data input pin of LSI, whereby the register outputs the data to each testing circuit in the LSI to set each testing circuit to the testing condition for checking whether or not the LSI can operate correctly. Each testing circuit is controlled by the CPU through each pin of the LSI, a control bus. The testing circuits the address bus, and transmits the data resulting from the test to the CPU through the data bus, so that the CPU can determine the functions of the LSI based on the data. Before LSIs are shipped from the factory, `0` the test mode switching pin of each LSI which has passed the above mentioned device test is made `0` which represents the normal operation mode, whereby the test signal data register is disabled, so that the LSI can work in the normal operation mode under the control of CPU.
The conventional LSIs of the above type necessitate an external pin serving as a test mode switching pin, to enable the LSIs in the test mode. LSIs are, however, limited in the number of external pins. Sometimes it is not feasible to provide even one test mode switching pin.
In the conventional LSI test mode switching device, there must be used a relatively large size LSI package to provide the test mode switching pin. The conventional LSI test mode switching device prevents a decrease in the package size.